In general, as the semiconductor industry continuously progresses towards larger scale integrated circuits, the geometrical shape of device is continuously reduced, and circuit density increases to improve performance and reliability.
Because of this, thin layers of copper are used as a material for the metal interconnections in semiconductor devices. A copper wiring layer has a higher melting point than aluminum so that it presents higher resistance against electro-migration (EM), thereby improving the reliability of the semiconductor device. Copper has a low resistivity, allowing an increase the signal transmission speed. For these reasons copper wiring layers are used as interconnections suitable for an integrated circuit.
With closer spacing and higher speeds, parasitic capacitance between interconnections becomes a problem. When parasitic capacitance increases, the product of resistance and capacitance (RC) increases, which determines a time delay in circuit switching. Also, power consumption increases, and noise caused by mutual interference is generated, so that the device may be prevented from operating at high speed. Therefore, an insulating material having a low dielectric constant value (low-k), no more than 3, for example, a porous oxide, is used as an interlayer dielectric layer.
In fabricating interconnections using copper and low-k insulating material, the poor etchability of copper makes a dual damascene process a favorable solution. The dual damascene process has four methodological variations using 0.13 μm design rules, categorized as buried via, via first, trench first, and self aligned processes.
Increasing the speed of CMOS logic devices mainly depends on reducing gate delay time caused by reduction in a gate road. However, the speed of the device depends on RC delays caused by back end of line (BEOL) metallization in highly integrated devices.
In order to reduce the RC delay, low resistivity copper is used to form the metal interconnection (reducing resistance), and the interlayer dielectric layer is formed by using a low-k dielectric material (reducing capacitance), and then dual damascene process is adopted.
FIGS. 1A to 1E are sectional views illustrating a method of forming a related dual damascene pattern.
Referring to FIG. 1A, a first insulating layer 100 and a first conductive layer 102 is formed over a semiconductor substrate (not shown), which has undergone a conventional semiconductor manufacturing process. A second insulating layer 104 is deposited and the resultant structure is coated with a first photoresist 106 for a photolithography process. FSG or P—SiH4 oxide, for example, can be used as the second insulating layer 104.
In FIG. 1B, a first photoresist pattern, that is, a via hole photoresist pattern 106′ is formed over the resultant structure of FIG. 1A through a photolithography process. The second insulating layer 104 is etched using the via hole photoresist pattern 106′ as a mask to form a via hole 108.
Then, in FIG. 1C, after removing the via hole photoresist pattern 106 of FIG. 1B, the resultant structure is coated with a second photoresist (not shown) and a photolithography process is performed on the second photoresist to form a second photoresist pattern 110. Then, the second insulating layer 104 is etched using the second photoresist pattern 110 as a mask to form a trench 112.
In FIG. 1D, the second photoresist pattern 110 patterned over the resultant structure of FIG. 1C is removed and a second conductive layer 114 is deposited over the resultant structure to fill the via hole and the trench 112. Copper, including a barrier metal layer, can be applied as the second conductive layer 114.
Finally, in FIG. 1E, a chemical mechanical polishing (CMP) process is performed so to planarize the second conductive layer 114, leaving copper only in the via hole 108 and the trench 112 to form a via contact unit 116 and an interconnection unit 118.
According to a related dual damascene process, in order to reduce resistance, a copper interconnection is used. In particular, a low dielectric constant layer and the copper interconnection are combined to improve the performance of the device.
In a related semiconductor device, a repair fuse is provided to repair the interconnection. To keep the process simple, the metal layer used for the interconnection is shared with the fuse.
Therefore, in semiconductor devices that use copper interconnections, the copper may be used for the repair fuse as well as for the interconnection.
In devices where the repair fuse is formed of copper, it is possible to cut the repair fuse using laser light. After the cutting process, in order to test which memory cells are good, a bias voltage is applied to the cut part of the repair fuse.
Since the severed portion of the fuse is then exposed to the air, corrosion may be caused by moisture. The bias voltage and the insulated part caused by cutting can be connected. As a result, a device characteristic degrades so that semiconductor yield degrades.